In silicon on insulator (SOI) technology a thin silicon layer is formed over an insulating layer, such as silicon oxide, which in turn is formed over a bulk substrate. This insulating layer is often referred to as a buried oxide (BOX) layer or simply as a BOX. For a single BOX SOI wafer the thin silicon layer is divided into active regions by shallow trench isolation (STI) which intersects the BOX and provides a total isolation for active device regions formed in the silicon layer. Sources and drains of field effect transistors (FETs) are formed, for example, by ion implantation of N-type and/or P-type dopant material into the thin silicon layer with a channel region between the source and drain using the gate pattern to self-define the channel region. Prior to the formation of sources and drains gates can be formed on top of the channel region, for example, by deposition of a gate dielectric and conductor on the top surface of the thin silicon, followed by photolithographic patterning and etching. Back gates can also be formed under the active region on a single BOX SOI wafer using the BOX layer as the back gate dielectric. The back gates can be defined by, for example, either P+ or N+ implantation.
Transistors having back gates typically use relatively thin silicon and BOX layers to enable fully depleted device operation with a threshold voltage which is responsive to the back gate. Such FETs built in thin SOI technology with back gates can exhibit significant advantages such as, for example, reduced short channel effects, less threshold variability due to body doping fluctuations, and an ability to use the back gate voltage to adjust the threshold.
An embedded dynamic random access memory (eDRAM)) is a dynamic random access memory (dynamic or power-refreshed RAM) that includes some amount of static RAM (SRAM), where at least some memory accesses will be to the faster SRAM.